A two-dimensional optical phased array, or beam former, can for example be used in an infra-red counter measures (IRCM) system, for directing a high-power beam of potentially multi-band light at the optical aperture of a threat to dazzle and jam its optical seekers. These phased arrays can therefore improve the survivability of military and commercial platforms under attack from threat munitions and missiles that may be guided by a variety of electro-optic (EO) and infrared (IR) seeker types, such as semi-active laser (SAL) designator sensors and EO/IR imagers that sense one or multiple wavelength bands, with these seekers often sharing the same optical aperture. For at least these reasons, two-dimensional optical phased arrays are of interest to providers of military and commercial aircraft, as well as to any commercial developer of IRCM systems for military and civilian applications.
A two-dimensional optical phased array can also be used in compact laser radar systems. Such systems are used as altimeters for aircraft (including rotorcraft). Such systems also are envisioned for some automobiles. An advantage of a phased array is its large field of regard and fast beam steering, which means that one phased array could take the place of 4 to 10 or more small mechanical or micro-electro-mechanical (MEM) beam steerers.
FIG. 1 illustrates a known optical phased array 10 using optical-waveguide devices to accomplish phase shifting and amplitude adjustment of light from a light source 12, such as disclosed in: “T. E. Dilon, C. A. Schuetz, R. D. Martin, D. G. Mackrides, P. F. Curt, J. Bonnet, and D. W. Prather, “Non-mechanical Beam Steering Using Optical Phased Arrays,” Proc. of SPIE, Vol. 8184, 81840F, pp. 1-11, 2011”.
A linear array of optical-waveguide phase shifters 20 placed side by side provides phase shifts of light from light source 12, after it is split by an optical splitter 22. Optical waveguide phase shifters achieve a 0 to 2a range of phase shift in one phase shifter by controlling a voltage or current applied to the electrodes of the phase shifter.
A series of high output power optical amplifiers 30 is provided to adjust the amplitude of the output of each phase shifter 20. Flexible optical fibers 40 connect each output of amplifiers 30 to an optical emitter output aperture 42 of an emitter surface 44 that comprises a desired two dimensional pattern of emitter output apertures.
FIG. 2 illustrates a front view of an emitter surface 44 having a desired two dimensional pattern of emitter output apertures 42 as illustrated in FIG. 1. Emitter output aperture 42 are arranged along a non-uniform spacing on surface 34 to eliminate the dominant grating lobes and reduce the larger side lobes of the phased array.
An important limitation of using optical fibers is that the minimum spacing between adjacent emitter is then very large and thus the average side lobe power is fairly high. Also, since the size of the optical mode in a fiber is large compared to the wavelength of the light, the field of regard is very small (approximately 1 degree). For at least the above reasons, achieving a two-dimensional optical phased array using one or more mono-dimensional arrays of phase shifters and capable of steering an output optical beam over a large field of regard (e.g.,)±45-60° along two orthogonal axes has been difficult.
Another deficiency of known phased arrays such as phased array 10 is that the phase of the light output from the fibers 40, 48 can fluctuate as a result of mechanical vibrations or changes in ambient temperature, thus detrimentally affecting the operation of optical phased array 10.
A two-dimensional optical phased array 71 that consists of a stack of one-dimensional optical phased array slices 72 is illustrated in FIG. 3A. Such two-dimensional optical phased array is described in an article by A. Hosseini, D. Kwong, Y. Zhao, Y.-S. Chen, F. Crnogorac, R. F. W. Pease, and R. T. Chen, “Unequally spaced waveguide arrays for silicon nanomembrane-based efficient large angle optical beam steering,” IEEE J. Selected Topics in Quantum Electronics, Vol. 15, No. 5, pp. 1439-1446, 2009. Each slice 72 of the array consists of a silicon nanomembrane, with a suggested approach for constructing an assembly of multiple slices being a nanomembrane transfer technique described in an article by W. Peng, et al., “Single-crystal silicon/silicon dioxide multilayer heterostructures based on nanomembrane transfer”, Applied Physics Letters, Vol. 90, pp. 183107-1-183107-3, 2007. As described in the article by Peng, et al., a silicon nanomembrane is formed by etching the silicon dioxide layer of a silicon-on-insulator chip in an acid solution, to separate the thin silicon membrane layer from its initial silicon substrate. The membrane rises to the surface of the solution, at which point it can be transferred to de-ionized water for rinsing and then be lifted out of the water bath with a desired final substrate. After the remaining water evaporates, the membrane adheres to the final substrate to which it has been transferred. This process can be repeated to form a stack of multiple nanomembrane layers. Spin-on-glass can be deposited onto each of the transferred nanomembrane layers to separate that layer from a subsequent nanomembrane layer. Each silicon nanomembrane layer can be quite thin, with a thickness of approximately 100 nm reported in the paper. Optical phased array elements 73 can be formed on the nanomembrane layer, with control contacts 74 arranges on the edge of the nanomembrane layer.
FIG. 3B illustrates a known two-dimensional RF phased array assembly 60 having a two-dimensional array 62 of RF emitters 64. This assembly 60 is described in an article by L. Schulwitz and A. Mortazawi, “A Tray Based Rotman Lens Array with Beamforming in Two Dimensions for Millimter-Wave Radar,” IEEE Intl. Symposium on Phased Array Systems and Technology (ARRAY), pp. 850-853, October 2010″. Assembly 60 comprises a plurality of mono-dimensional phased array boards 66 that are placed on top of each other. The RF phase array assembly depicted in FIG. 3B illustrates two important features of a two-dimensional phased array assembly. The features are, first, a means to provide a mechanical support structure that defines and establishes the relative locations of the emitters of the phased array, and especially the placement of the boards of the array. A second feature is a means to provide for and connect electrical control signals to the boards of the assembly that determine the relative phase and amplitude of the radiation emitted by their emitters. In assembly 60, the boards 66 are secured at one end to a first mechanical structure supporting array 62 and at an opposite end to a second mechanical structure 68. Array 62 and structure 68 are secured to a base 69. Each board 66 comprises a Rotman lens 70 with a mono-dimensional array of outputs (not shown) connected each to an emitter horn antenna 64 of array 62. The electrical connections to each of the boards 66 are made by means of wires (not shown) that are connected to the side edges of boards 66. It is noted that the prior optical phased array assembly of the article by Hosseini et al. cited above can likewise have its electrical connections made to the side edges of its silicon nanomembranes. However, the feature of having a set of wires connected to the side of each board of a two-dimensional assembly, which proved suitable for a RF array that requires only a small number of elements in each boards and only a few boards, is difficult to implement in an optical phased array. For example, to achieve a narrow output optical beam and also high beam efficiency (high ratio of the power in the main beam compared to the total emitted power), an optical array must have many elements in each board, or slice, and many slices. Constructing an assembly having the necessary number of wires and connecting said wires to an electronic phase-control processor proved difficult.
Although the article by Hosseini, et al. does not discuss ways to provide the electrical interconnections to the layers or slices of the two-dimensional array, it does mention that the challenges for achieving the multi-level, stacked phased array structure are similar to the problems presently faced by those developing three-dimensional electronic integrated circuitry.
One prominent way to achieve a three-dimensional electronic integrated circuit is described for example in an article by A. W. Topol, et al., “Enabling technologies for wafer-level bonding of 3D MEMS and integrated circuit structures,” Proceedings 54th Electronic Components and Technology Conference, pp. 931-398, 2004. In such an approach, a three-dimensional circuit comprises multiple layers or chips of conventional planar electronic integrated circuits that are formed in the device layers of a silicon base substrate. The chips that contain the electronic devices and the integrated circuits are then bonded on top of each other, by removing the initial base substrates of silicon on which those integrated circuits were fabricated and using glass temporary-carrier (or handle) wafers to transport the chips for bonding to the stack. After one face of a chip is attached to the stack, the handle wafer of the chip is detached from the other face of that chip. A direct wafer-to-wafer bond by means of intermolecular Van der Waals attractive forces between oxides followed by annealing can be used to attach the chips to each other. After two chips are attached, vertical interconnects can be formed between those chips. The process steps for making the vertical electrical connections between bonded chips by etching deep via holes that are subsequently filled with metal is for example described in an article by J. A. Burns, et al., “A wafer-scale 3-D circuit integration technology,” IEEE Trans. Electron Devices, Vol. 53, pp. 2507-2516, 2006.
Instead of forming the electrical interconnections between the multiple chips after those chips are attached to each other, it also is possible to form those electrical interconnections as part of the attachment and bonding process for successive chips, as described for example in an article by J. J. McMahon, E. Chan, S. H. Lee, R. J. Gutmann and J.-Q. Lu, “Bonding interfaces in wafer-level metal/adhesive bonded 3D integration,” Proc. 2008 Electronic Components and Technology Conference, pp. 871-878, 2008. The structures described in this article require that metal pads be formed on both the top and bottom faces of each chip to facilitate the electrical connections made between adjacent chips. A combination of benzocyclobutene (BCB) and copper (Cu) bonds is used to attach a chip to an adjacent chip of this assembly. BCB is a fairly flexible and conformal adhesive and thus can accommodate moderate-height steps in the overall profile of a chip. However, the quality of the metal bond can be compromised by using BCB that has been only soft-baked prior to bonding. A less conformal partially cured BCB is preferred. It also is possible to use a combination of an oxide region and a metal region on each face of the chips to be bonded, as taught for example in articles by P. Enquist, et al., “Low cost of ownership scalable copper direct bond interconnect 3D IC technology for three dimensional integrated circuit applications,” 2009 IEEE Intl. Conf. on 3D System Integration, 2009 and by P. Enquist, “Scalable direct bond technology and applications driving adoption,” 2011 IEEE Intl. 3D System Integration Conference (3DIC), p. P-1-6, 2012. Besides using copper, other metal-to-metal bonds such as nickel-to-nickel or gold-to-gold also have been done in combination with oxide-to-oxide bonds. In general, the quality of the bond can be improved by heating the bonded pieces to a somewhat higher temperature, such as 350° C. One problem arising with such higher temperature bonding is that the compression steps of the bonding are likely to distort the thickness of the chips manufactured as suggested in the above-cited references.
In the structures described by the above-cited McMahon and Endquist references, the electrical interconnections from one chip to the next and through multiple chips follow a winding path. It is noted that there is no straight metal path that extends from the base of the assembly and through the multiple chips. It is also noted that these 3D electronic integrated circuits do not contain any mechanical framework or structure that defines the physical spacing between its layers.
For an optical assembly that comprises a two-dimensional emitter array of a phased array formed out of a chip/slices stack, it is often desirable for the relative locations of the chips in the stack to be controlled to a precision of approximately λ/10 or better, where λ is the wavelength of the light in the beam formed and steered by the phased array. This means, for example, that if λ=1.5 μm, the relative spacing of the chips should be controlled to an accuracy of 0.15 μm or better.
The inventors have noted that the compression steps of higher temperature bonding as disclosed above are likely to distort the thickness of chips manufactured as suggested in the above-cited references when assembling chip stack to manufacture a two-dimensional emitter array, thereby possibly affecting the performances of said emitter array in a detrimental manner.
Further to the above considerations, the inventors have also noted that, for an optical assembly, there is a need for the assembly to be sufficiently rigid that mechanical vibrations and moderate changes in temperature will not significantly change the spacing between the array emitter elements. Chips produced and assembled as suggested in the above-cited references on electronic 3D integrated circuits do not provide this desired mechanical rigidness.
There exists a need for a two-dimensional optical phased array comprised of elements such that the assembly of the elements does not detrimentally affect the operation of the optical phased array. There also exists a need for a method for manufacturing such a two-dimensional optical phased array.